1. Field of the Invention
The present invention relates to a storage system with a data recovery function and its method, and more particularly to a system and a method for testing a memory and correcting data by writing test data into an address of error data for one or more times.
2. Description of Related Art
As flash memories offer faster access speed, less power consumption, smaller volume and better shock resistance than traditional hard disks, flash memories are used extensively in information storage devices.
Due to the structure of the flash memory, stored data may have errors caused by the interference of high voltage and the deterioration or damage of a memory cell. For instance, the original state of a memory cell is of high potential, but the controller reads a low potential of the memory cell, or the original state of a memory cell is of low potential, but the controller reads a high potential of the memory cell.
To prevent errors of the data stored in the flash memory and enhance the reliability of the stored data, the prior art uses an error checking and correction (ECC) technique for detecting and correcting error data.
The ECC technique is described briefly as follows. When data is written into a flash memory, the data is computed by an ECC unit of a memory controller to generate an ECC code of the data, and the ECC code together with the data are stored in the flash memory. When the data is read, the controller reads the data and the ECC code, and the ECC unit executes the operation of checking and correcting an error bit. If no error bit is found in the checking operation, then the data will be outputted. If an error bit is found in the checking operation and the number of error bits falls within a range recoverable by the ECC technique, then the data will be outputted after a correction is made. If the number of detected error bits exceeds the range recoverable by the ECC technique, then the controller will report an error of reading data.
Related checking and correction methods for the data stored in a flash memory are disclosed in U.S. Pat. Publication No. 20040230879 entitled “Apparatus and method for responding to data retention loss in a non-volatile memory unit using error checking and correction techniques” and issued on Nov. 18, 2004, and U.S. Pat. No. 6,785,856 entitled “Internal self-test circuit for a memory array”, issued on Aug. 31, 2004. The former issued patent provides an error detection and recovery method for error bits of a flash memory recoverable by the ECC technique, and the later issued patent provides a test circuit installed in a storage system for detecting error bits in a memory as shown in FIG. 1.
With reference to FIG. 1 for a memory device 100 having a self-tester 104 disclosed in U.S. Pat. No. 6,785,856, a memory unit 102 is connected to the self-tester 104 comprising an error checking and correction (ECC) circuit 106, a self test circuit 108, and a register 110. The memory unit 102 comes with a memory structure divided into several memory pages. The self-tester 104 is responsible for detecting and correcting an error in the memory. The ECC circuit 106 is provided for checking each memory page by groups, and a cyclic redundancy check (CRC) method of the Reed-Solomon algorithm is used for detecting the errors in the memory unit, and the self test circuit 108 is provided for counting the number of errors in the memory and storing the number of errors in a buffer area 110, and different data tests for an access state of each memory bit are used for the data correction.
In the aforementioned prior art, the error of reading data still occurs if the number of error bits exceeds the range recoverable by the ECC technique.